The present invention relates to a semiconductor memory device with a redundancy circuit and a technique for reading redundant addresses in a semiconductor memory device equipped with redundant memory cells.
A semiconductor memory device is equipped with redundant memory cells each of which relieves a memory area of a defective or fail memory cell caused by a defect or the like in a process step in order to enhance yields. When a defect is found in an inspection step after package encapsulation and a malfunction has occurred on the customer's premises, there is also a need to examine the relationship between a defective address and its corresponding redundant memory cell upon its defective analysis. This is because only an inspection much looser than an inspection for a normal memory cell has been effected on the redundant memory cell in a pre-replacement probing process. That is, this is because a problem arises where a defect occurs in a redundant memory cell that should haven been replaced to relieve a defective memory cell.
The following two methods have heretofore been used as a method of examining a redundant address after package encapsulation. One of them is a method of making a package open and visually confirming a fuse cut off to set a redundant address. The other thereof is a method of incorporating a test circuit in advance and setting a test mode thereby to allow an output terminal to output information about cutting-off of a fuse.
However, the method of making the package open is accompanied by a problem that the package is broken. Also the method of allowing the output terminal to output the cut-off information of the fuse needed a signal path for reading the cut-off information of the fuse, i.e., a dedicated wiring extended from a fuse to a data bus. Therefore, a problem arose in that the area of a chip would increase because of the dedicated wiring.